One or more embodiments relate generally to a method of manufacturing a semiconductor device and, more particularly, to a method of forming the patterns of a semiconductor device that is capable of making micro intervals between conductive patterns of a semiconductor device.
For highly-integrated semiconductor devices, the design rule of the semiconductor devices is abruptly decreased. With such a reduction in the design rule of the devices, intervals between patterns constituting the semiconductor device become micro in scale. In general, the shape of the patterns constituting the semiconductor device is determined by the shape of a photoresist pattern formed through a photolithography process. The photolithography process has reached a limit in making micro the pattern pitch of the semiconductor device because of limited exposure resolution. To overcome limited exposure resolution, spacer patterning technology is used.
In spacer patterning technology, auxiliary patterns are formed at specific intervals using a photolithography process, and a spacer is formed on sidewalls of the auxiliary patterns. Here, the spacer surrounds the auxiliary pattern. To separate the spacers into individual line patterns, a mask process and an etch process are performed.
The mask process is used to form first hard mask patterns for blocking portions that will become the individual line patterns of the spacer and for opening portions that should be removed in order to separate the spacer into the individual line patterns. The etch process is performed to etch the spacers using the first hard mask patterns as an etch barrier.
If the spacers that are separated into the individual line patterns by the mask process and the etch process remain, a hard mask layer beneath the spacers is etched using the remaining spacers as an etch barrier, thereby forming second hard mask patterns. Next, the patterns of the semiconductor device are patterned using the second hard mask patterns as an etch barrier. Here, the spacers remaining as the line patterns on both sides of each auxiliary pattern can have different widths.
Accordingly, odd-numbered lines and even-numbered lines of the patterns of the semiconductor device formed using the remaining spacers can have different widths. Further, the process is complicated because the additional hard mask layer must be formed in order to separate the spacer into the individual lines. In addition, the hard mask layer can have a failure when forming the hard mask layer because the mask layer has a stack structure of a number of layers. Moreover, a defect can occur in the pattern because of deterioration in adhesion characteristic between layers. Furthermore, a problem arises in that the spacer patterns or the hard mask patterns collapse during the patterning process due to deteriorated adhesion characteristics resulting from a reduced contact area of the spacer, the hard mask pattern, and an underlying layer according to the high degree of integration of the semiconductor device.